Photocurrent Compensation Techniques for Radiation Hardening of Integrated Circuits.
Final rept. May 67-Aug 68,
HUGHES AIRCRAFT CO FULLERTON CA
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The objective of the program is To determine the applicability of and benefits to be derived from diode and transistor photocurrent compensation for integrated circuit hardening in a transient radiation environment. The program is divided into two phases where Phase 1 explores the techniques of photocurrent compensation. Critical device parameters were selected which affect photocurrent generation. Devices were fabricated with controlled variations of these critical parameters. These devices were subsequently tested in radiation environments. Data are presented on photocurrent matching and tracking. Analyses were performed for RTL, DTL and TTL gate circuits. The RTL and TTL analyses are presented in the report. A simple inverter circuit was wired out of the test devices and determined hard to 5 x 10 to the 9th power radSisec. Phase 2 objectives were to utilize the results of Phase 1 to fabricate a hardened TTL NAND gate. The TTL gate was fabricated using dielectric isolation, thin film resistors, minimum geometry devices, and normal integrated circuit processing methods. The gate was radiation tested and found to be hard to 1 x 10 to the 10th power radSisec. Author
- Electrical and Electronic Equipment