Several Stochastic Models of Computer Systems.
STANFORD UNIV CALIF STANFORD ELECTRONICS LABS
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The author analyzes a CPU executing more than one instruction during a memory cycle and making requests to an interleaved memory system. The analysis leads to an expression for the expected number of instructions executed per memory cycle in terms of the degree of interleaving, the maximum number of instructions executed per memory cycle and the parameters representing the program behavior. It is observed that the use of memory interleaving increases the throughput by a factor of, at most, two. Queueing networks and sequences of queueing centers are analyzed when the queues have finite capacity. Open and closed queueing networks with different priority classes of customers and general service time and arrival time distrubutions, depending on the priority class of the customer and the service center. Finally, the effects of the distribution of service time and the length of the quantum on the mean waiting time for different quantum controlled service disciplines are studied. Modified author abstract
- Computer Hardware
- Computer Systems