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A Study of Electronics Radiation Hardness Assurance Techniques. Volume III. Lot Sampling and Irradiate-and-Anneal.
Final rept. 31 Jul 70-16 Jul 73,
BOEING CO SEATTLE WASH
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The program determined physical failure modes of a range of discrete and integrated semiconductor devices exposed to ionizing rate, neutron, and total dose environments. The efficacy of lot sample radiation testing was evaluated using transistors with traceability as far back as wafer position. In addition to studing homogeneity at a wafer level and between wafers, the variability between diffusion runs was assessed. Base transit time normalization for the low-power transistors reduced the measured variability in neutron damage across the wafers, and betwen diffusion lots. This result establishes the existence of a reasonable degree of homogeneity for the low-power devices studied. Inhomogeneity of surface effects at wafer and diffusion levels was established for the transistors used in this task. Irradiate-anneal, IRAN, for parts subjected to neutron and total dose environments was evaluated. Neutron IRAN for the power transistor was found to be an effective technique as determined by the predictability of the neutron induced gain degradation. otal dose IRAN was effective for the op amp used, butt inadequate for the sense amp which was extremely hard. Modified author abstract
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