Analytic Models for Memory Interference in Multiprocessor Computer Systems
CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE
Pagination or Media Count:
The thesis develops analytic models for estimating the amount of memory interference in multiprocessor systems, in which n processors access m memories independently. The processors are characterized by a typical processing time per memory access and the memories by an access time and rewrite time. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing. The predominant technique used involves discrete time Markov chain models. Some simple exponential server models as well as several approximate models are also presented. Simulation is used to evaluate the accuracy of the approximate models. Some empirical measurements of the PDP-1120 are used to estimate the parameters of a model, that is used to predict the performance of C.mmp, Carnegie-Mellon Universitys multiprocessor computer, which will include up to 16 PDP-11 processors.
- Computer Hardware