Accession Number:

AD0773098

Title:

Analysis and Simulation of Parallel Sequential Decoding.

Descriptive Note:

Technical document,

Corporate Author:

NAVAL ELECTRONICS LAB CENTER SAN DIEGO CALIF

Personal Author(s):

Report Date:

1973-10-29

Pagination or Media Count:

72.0

Abstract:

The document describes the implementation of a sequential decoder on a PDP-11 computer and presents a preliminary evaluation of decoder performance using a buffer allocation scheme modified to improve the use of buffer memory to minimize the probability of overflow. The modified decoder consists of two decoding processors operating on two half-size buffers. Input blocks are placed in the first available buffer, thus allowing a noisy block to remain in a buffer for a longer period than would normally be available with a single buffer and processor. A net gain for the modified system, due to lower probability of failure caused by buffer overflow, is indicated. Author

Subject Categories:

  • Cybernetics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE