On Generating Near Minimum Test Sets.
AUBURN UNIV ALA DEPT OF ELECTRICAL ENGINEERING
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A computerized algorithm for generating near minimum test sets for fault detection in combinational logic circuits is presented. The advantages of the approach in this algorithm over classical techniques are shown. The algorithm is then described and illustrated in great detail. Two software implementations of the algorithm are also given. Finally, comparisons and contrasts between this algorithm and other similar ones are described. Author
- Electrical and Electronic Equipment
- Computer Programming and Software