Accession Number:

AD0765037

Title:

Self-Checking of Multi-Output Combinational Circuits using Forced-Parity Technique.

Descriptive Note:

Doctoral thesis,

Corporate Author:

UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES ELECTRONIC SCIENCES LAB

Personal Author(s):

Report Date:

1973-06-01

Pagination or Media Count:

159.0

Abstract:

One integral part of a self-checking system is an appropriate error detecting circuit. The error signal provided can be used to stop computation, signal for manual repair, or initiate automatic reconfiguration. In the report error detecting schemes for combinational circuits are investigated from the hardware redundancy viewpoint. It is well-known that any circuit can be checked by the technique of complete duplication. The redundancy ratio obtained is higher than 21. The technique presented in this dissertation is called Forced-Parity Checking. Its concept is derived from conventional parity checking technique which is applicable only for odd numbers of errors, yet it can detect errors of any degree. Since some circuits lend themselves to be checked more efficiently by one technique than by another, this technique is by no means expected to achieve a low redundancy ratio for every circuit. The main objective is to generalize and formalize a design procedure which, when applied to a circuit, may yield a redundancy ratio below the known lower bound. Modified author abstract

Subject Categories:

  • Electrical and Electronic Equipment
  • Manufacturing and Industrial Engineering and Control of Production Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE