MOS Threshold Logic II.
Final technical rept. Dec 71-Dec 72,
RCA GOVERNMENT COMMUNICATIONS SYSTEMS SOMERVILLE N J ADVANCED COMMUNICATIONS LAB
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The program represents the second phase in the Development of MOS threshold logic. Studies were made previously, indicating the limitations and applications of MOS threshold gates. Now, threshold gates were integrated for use in parallel array multipliers as well as for general logic synthesis. Two approaches were taken in CMOS technology an analog and a functional design. The analog threshold gates consist of arrays of inverters and take dc power, by design. A 1X8 adder matrix was integrated for use in multipliers and, although the principle of the logic was demonstrated, a basic restriction was uncovered. The functional approach is based on a more conventional return to preserving all the advantages of CMOS and many of the advantages of threshold logic. A 4X4 adder array was integrated to demonstrate this approach and a multiplier breadboard was built to demonstrate the chips. Author
- Electrical and Electronic Equipment