Study of Multiprogrammed Computer Systems with Memory Hierarchies.
TEXAS UNIV AUSTIN ELECTRONICS RESEARCH CENTER
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The possibility of using queueing networks to study the performance of multiprogrammed computer systems that use memory hierarchies was investigated. It was found that these kinds of models are adequate provided the success function of the memory hierarchy is known. A stochastic algorithm to obtain the success function of the hierarchy was developed. The results obtained, whenever this model is used in conjunction with the queueing network, were extensively compared with conventional simulation techniques, and the accuracy found to be within five percent. The problem of scheduling the Central Processor was considered, and empirical algorithms to determine policies that set upper and lower bounds on the success function of the hierarchy were proposed. Mathematical methods were employed to analyze various system configurations, that include several input-output channels and processors. Author
- Computer Hardware