Accession Number:

AD0745742

Title:

A Class of Testable Gate Network Realizations for Logic Functions.

Descriptive Note:

Technical rept.,

Corporate Author:

IOWA UNIV IOWA CITY DEPT OF MATHEMATICS

Personal Author(s):

• Reddy,Sudhakar M.

Report Date:

1972-05-01

Pagination or Media Count:

17.0

Abstract:

By assuming that the functions realized by certain subnetworks of certain gate networks realizing an arbitrary logic function are known, techniques to derive tests to detect faults in these networks are derived. Author

Descriptors:

• *LOGIC CIRCUITS
• *GATES(CIRCUITS)
• COMPUTER LOGIC
• BINARY ARITHMETIC
• VECTOR SPACES
• SET THEORY
• THEOREMS

Subject Categories:

• Electrical and Electronic Equipment
• Theoretical Mathematics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE