Accession Number:

AD0745741

Title:

Techniques for the Design of Two-Level Fault-Tolerant Logic Networks.

Descriptive Note:

Technical rept.,

Corporate Author:

IOWA UNIV IOWA CITY DEPT OF MATHEMATICS

Personal Author(s):

• Pradhan,Dhiraj K.
• Reddy,Sudhakar M.

Report Date:

1972-05-01

Pagination or Media Count:

35.0

Abstract:

A technique for the synthesis of fault-tolerant combinational networks is presented. The novelty of the technique lies in the framework in which the problem is formulated. Necessary conditions for the synthesis of two-level networks tolerating stuck-at type faults are developed. It is shown that there exists a significant difference between the conditions that have to be satisfied for the synthesis of networks in which only internal faults are masked and in which both internal and primary input faults are masked. As a result, it is established that certain normally assumed conditions are too strong. Design techniques are presented for the synthesis of networks tolerating all types of faults except the faults which change the output to the constant function. A class of hazards is defined. It is shown that the synthesis of certain hazard-free realizations is equivalent to the fault-tolerant realization. Author

Descriptors:

• (*LOGIC CIRCUITS
• SYNTHESIS)
• GATES(CIRCUITS)
• RELIABILITY(ELECTRONICS)
• SWITCHING CIRCUITS
• MATHEMATICAL LOGIC
• MATHEMATICAL MODELS
• CODING
• THEOREMS

Subject Categories:

• Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE