Accession Number:

AD0744269

Title:

Plan and Analysis of Binary Synchronous Counting Circuits,

Descriptive Note:

Corporate Author:

FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OHIO

Personal Author(s):

• Mueller,F.

Report Date:

1972-04-04

Pagination or Media Count:

15.0

Abstract:

The article reviews the basic principle of synchronous counters, which are a special case of autonomous sequential switching circuits. The design of such counters requires a minimization of combinatorial networks with several inputs and several outputs. A three-step procedure is shown by which a binary counter can be designed with JK-type flip-flops, rather than with D-Type flip-flops, to yield the simplest circuits. The procedure involves the use of Karnaugh maps and state tables. Coding and truth table are also shown. The performance is analyzed by means of state diagrams containing nodes and arrows appropriately related. Author

Descriptors:

• *LOGIC CIRCUITS
• SYNCHRONIZATION(ELECTRONICS)
• COMBINATORIAL ANALYSIS
• SHIFT REGISTERS
• EAST GERMANY
• RELAXATION OSCILLATORS

Subject Categories:

• Electrical and Electronic Equipment
• Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE