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Plan and Analysis of Binary Synchronous Counting Circuits,
FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OHIO
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The article reviews the basic principle of synchronous counters, which are a special case of autonomous sequential switching circuits. The design of such counters requires a minimization of combinatorial networks with several inputs and several outputs. A three-step procedure is shown by which a binary counter can be designed with JK-type flip-flops, rather than with D-Type flip-flops, to yield the simplest circuits. The procedure involves the use of Karnaugh maps and state tables. Coding and truth table are also shown. The performance is analyzed by means of state diagrams containing nodes and arrows appropriately related. Author
APPROVED FOR PUBLIC RELEASE