Semiannual technical summary rept. 1 Dec 1970-31 May 1971
MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB
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The hardware for the Terminal Support Processor TSP system is in various stages of design, construction, and checkout. The two Digital Scientific Corporation Meta 4 microprocessors and main memory system have been delivered, but acceptance awaits the installation of revised memory controller and central processor boards. The secondary memory has been delivered to the interface vendor, and the interface has been checked out on a single processor system. A multichannel controller which will simplify the interfacing of the other peripheral equipment has been constructed and tested. A serial transmission and time multiplexing scheme for handling keyboards and console indicators has been designed. The design uses a standard TV composite video signal. Two minimal console stations have been built and tested. Error rates appear to be satisfactory for this application. TSP software effort has concentrated on developing the support facilities which run on TX-2 and handle assembly and compilation for the TSP. Code generators for a BCPL compiler for the BCOM machine, the processor for system software in the TSP, are being debugged and indicate good efficiency of compiled code. Diagnostics for the BCOM machine have been written and debugged on the Meta 4 simulator on TX-2 and have been tested satisfactorily in the Meta 4 system.
- Computer Programming and Software
- Computer Hardware
- Computer Systems