Efficient Generation of Minimum Fault Test Schedules for Combinational Logic Networks.
AUBURN UNIV ALA
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A number of fault detection procedures for combinational logic networks are discussed and efficient algorithms are developed for the automatic generation of network test inputs. Each of the algorithms is specialized in the sense that each is designed to generate tests for a specific class of logic networks. The analysis and development of the algorithms is based on the assumption of a single error in the form of a struck-at-one or struck-at-zero fault. Algorithms are also included which can be used for no-fan-out networks, sum-of-products and product-of-sum networks, and factored realizations. Test schedules generated by the computer-aided procedures provide both a complete and minimum set of test inputs for the different types of logic networks considered. Author
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