Accession Number:

AD0726382

Title:

A Logic Design Procedure to Facilitate Fault Detection.

Descriptive Note:

Thesis,

Corporate Author:

ILLINOIS UNIV URBANA COORDINATED SCIENCE LAB

Personal Author(s):

Report Date:

1971-06-01

Pagination or Media Count:

105.0

Abstract:

A procedure that combines the design of a logic network with the generation of fault detection tests is presented. Certain restrictions are placed on the allowable network structure to insure that the designed network is always diagnosable. The first step in the procedure is to reduce all functions to their prime implicants. An irredundant sum of prime implicants is then selected while fault tests are simultaneously generated. The resultant sum of prime implicants may then be realized in either a two level network for which the test set is sufficient to test all single and all multiple faults or in a multiple level network that satisfied the restriction and for which the test set is sufficient to test all single faults and in some cases all multiple faults. The results are expressed in a decimal numeric notation that is particularly adaptable to a computer implementation. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE