RESEARCH AND DEVELOPMENT OF HIGH SPEED PROCESSOR ARRAYS
Interim summary rept. no. 4, 22 Jul 1968-31 Oct 1969
MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB
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The report describes program progress for the first four interim periods of a research and development program directed toward the development of high density, high performance, complex digital arrays and their application in system feasibility studies of a high speed Central Processor. An important task of the program was to establish subnanosecond-minimum power ECL microcircuit designs which could be used as effective building blocks for the Processor Arrays. The task required the design, fabrication and evaluation of an array test chip containing different microcircuit designs. The task was accomplished specific small geometry gate and reference bias microcircuits gate power dissipation was nominally 15 mW, including complementary outputs were selected and utilized in the design of an 80-gate Processor Master Array Chip. Functioning high speed 256-bit Read only Memory Arrays were successfully fabricated. A flexible technique for programming these ROMs at the chip level was developed and demonstrated. Yield improvement studies were conducted.
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