A FAST, FLEXIBLE, HIGHLY PARALLEL ASSOCIATIVE PROCESSOR.
NAVAL RESEARCH LAB WASHINGTON D C
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The logical design and operation of a general purpose associative processor GPAP is described. The basic circuit consists of a powerful associative cell which may be combined with an integral number of identical cells and implemented in MSI or LSI at a reasonable cost. A complete description of this cell, together with logic diagrams, Boolean equations, and a detailed timing analysis are presented. The processor obtained by connecting these cells together in quantity has both variable syllable and variable instruction capability. That is, the total associative word length can be split on a software basis into any number of syllables fields, each of arbitrary length. The search criteria greater than, less than, greater than or equal to, less than or equal to, exact match, and dont care can be specified independently for each of these syllables. The search time depends only on the width of the largest syllable and is typically less than 1 microsecond assuming gate delays of approximately 20 nanoseconds. The problem of multiple responses priority resolution is considered in detail. The design of a high-speed, inexpensive in terms of the number of gates required per word response resolution network is presented. Other GPAP operations include conventionally addressed read, write, add, multiwrite, multiadd, and logical operations. Simultaneous operations, such as write-on-match and add-on-match, are also possible. These capabilities, as well as several other unique properties of the design which contribute to its general purpose character and high speed of operation are described in detail. Author
- Computer Hardware