Accession Number:

AD0694555

Title:

RESEARCH AND DEVELOPMENT OF HIGH SPEED PROCESSOR ARRAYS.

Descriptive Note:

Interim rept. no. 3, 22 Jan-21 Apr 1969

Corporate Author:

MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB

Personal Author(s):

Report Date:

1969-06-01

Pagination or Media Count:

23.0

Abstract:

Preliminary design for a processor master array chip containing 80 gates and 16 reference bias cells has been completed. Functioning read-only memory arrays were successfully fabricated. A flexible technique for programming these ROMs at the chip level has been developed and demonstrated. Speed-power studies aimed at obtaining optimum performance in the processor arrays are continuing. Yield improvement studies are continuing. This effort includes the investigation of the applicability of the CDI process to high-speed ECL and the design of a complex multilevel process test chip for characterizing and monitoring multilevel interconnection processes and structures. Test vehicles are being fabricated for investigating face-down bonding and aluminum beam lead technologies. Reliability data are presented for high-speed two-level arrays.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE