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RESEARCH AND DEVELOPMENT OF HIGH SPEED PROCESSOR ARRAYS
Interim rept. no. 2, 22 Oct 1968-21 Jan 1969
MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB
Pagination or Media Count:
The reported work was performed during the second interim quarterly period of a research and development program directed toward the development of high density, high performance, complex digital arrays and their application in high speed system feasibility studies. During this interim, high speed ECL microcircuit cells of several designs were fabricated and characterized. Specific gate and reference bias circuits were selected for use in the processor arrays. Development continued on high yield microcircuit and multilevel interconnection techniques. Preliminary design of a multilevel process evaluation chip was completed. Thermal studies of discretely packaged high power 1 watt LSI chips were made using a thermal test chip as a vehicle. Final design of a 256-bit read-only memory array was completed. The photomasks were all generated using computer aid.
APPROVED FOR PUBLIC RELEASE