A CYCLIC CHECK COMPUTER FOR ERROR DETECTION
MICHIGAN UNIV ANN ARBOR
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The report discusses the design and use of equipment built to aid intercomputer communicatitions via serial-synchronous data transmission techniques. The interface described computes on a character-by-character basis, a cyclic redundancy block checksum which is appended to outgoing or checked against incoming messages. This hardware techniques reduces checksum computation on a small computer from several hundred microseconds per character to only several microseconds a reduction that is necessary if more than several 201 type data modems are to be operated simultaneously under control of a single processor. Basic design objectives and decisions are described first. A brief overall system description with background information is then followed by programming considerations and detailed descriptions of the checksum computer logic. Finally diagnostic software and wirewrap documentation is provided for maintenance andor reproduction purposes.
- Computer Programming and Software
- Computer Hardware