Accession Number:

AD0647152

Title:

A STUDY OF AN ERROR DETECTING PARALLEL ADDER,

Descriptive Note:

Corporate Author:

ILLINOIS UNIV URBANA COORDINATED SCIENCE LAB

Personal Author(s):

Report Date:

1967-01-01

Pagination or Media Count:

65.0

Abstract:

The problem of reliability, in particular the detection, location, and correction of faults, has concerned those in the digital computer field from the very beginning. The difficulties arise essentially from the complexity of the electronic systems involved. Even though the failure probability of an individual component is minute, in such large systems the probability of a fault occurring somewhere may not be negligible. It is the purpose of the thesis to investigate the applicability of AN B codes to the detection of faults in arithmetic units. In the course of the discussion, a design for an adder and checking circuit using such a code is presented and analyzed. No attempt is made to correct errors once they have been detected. By such means as using NAND elements as the basic logical components, an attempt was made to make the design amenable to modern engineering practices. However, there are a few problems of a practical engineering nature which are pointed out but left unsolved. Author

Subject Categories:

  • Computer Hardware
  • Manufacturing and Industrial Engineering and Control of Production Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE