INTEGRATED LOGIC NETS.
Final rept., 1 Jul 64-30 Nov 66,
RCA LABS PRINCETON N J
Pagination or Media Count:
The use of thin single-crystal silicon films deposited on single-crystal sapphire has yielded the most promising solution to the fabrication of complex complementary-MOS transistor integrated circuits. High-performance 10-transistor memory cells exhibiting a switching speed of less than 12 nsec at a power dissipation of 10 microwatts have been fabricated on thin silicon films. In addition, a 90-transistor word cell has been fabricated which dissipates only 90 microwatts for the entire circuit. The fabrication of both N- and P-channel transistors on a bulk silicon substrate has been accomplished through use of a composite wafer in which alternate bars of P- and N-type silicon are isolated by a thick layer of silicon dioxide. In addition, a two-wafer scheme involving a novel face-to-face soldering technique has provided an alternate approach to fabricating complementary-MOS transistor circuits. The technology necessary to yield a low-capacitance two-level intraconnection scheme has been developed, which allows the use of most vacuum-deposited dielectrics for the insulating layer chemical etching of this layer is not necessary due to a novel technique used to introduce small holes in the insulating layer. Author
- Electrical and Electronic Equipment
- Computer Hardware