MODELS AND DATA STRUCTURES FOR DIGITAL LOGIC SIMULATION.
MASSACHUSETTS INST OF TECH CAMBRIDGE PROJECT MAC
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A digital logic simulation system is proposed for design verification. Logic to be simulated is specified with a high-level register transfer design language, and the simulation system operates on-line on a large time-shared computer. The problem of selecting adequate circuit and signal models for this purpose is considered. Models are proposed with sufficient timing detail to allow the simulation system to detect timing errors which currently are found by manual checking or prototype debugging. A data structure for representing idealized circuit and signal models and a matching simulation algorithm is discussed. The data structure is a direct representation of a complete subset of the design language and is organized so that it can be incrementally modified to reflect design changes. The simulation algorithm is very efficient because combinational levels are re-evaluated only if their values are needed and may have changed since last evaluated. The data structure is expanded to represent detailed circuit and signal models. A method of intermixing idealized and detailed models and efficiently simulating very large designs is discussed. Extensions are proposed to the design language so that it can be used to specify model parameters and serve as the simulation command language. Author
- Computer Hardware
- Computer Systems