INTEGRATED LOGIC NETS.
Interim rept., 1 Jul 64-28 Feb 66,
RCA LABS PRINCETON N J
Pagination or Media Count:
Investigations have been conducted into the technology necessary to interconnect arrays of n- and p-type MOS transistors into complementary-symmetry digital circuits. A memory module consisting of four n-type and four p-type transistors was chosen as the test vehicle. It is shown that first-level wiring on each array requires a blanket insulation between one and two microns thick to reduce wiring capacitance, and a scheme is described whereby access holes through any vacuum-deposited insulator may be obtained. The interconnection of the n-type and p-type arrays is accomplished by evaporating solder dots at appropriate points on each array, placing the arrays face-to-face, and heating in a reducing atmosphere to produce solder connections. Alignment is accomplished by looking through the silicon wafers with an infrared-to-visible light converter the wafers are illuminated from below with a Sun Gun which also serves as the heat source when intensity is increased. Author
- Electrical and Electronic Equipment
- Solid State Physics