PRODUCTION ENGINEERING MEASURE FOR SILICON OVERLAY TRANSISTORS.
Quarterly progress rept. no. 3, 1 Jul-30 Sep 65,
MOTOROLA INC PHOENIX ARIZ SEMICONDUCTOR PRODUCTS DIV
Pagination or Media Count:
Progress during the reporting period consisted of the following 1Diffusion systems. Work was completed on the BBr3 base diffusion system, and system feasibility was determined. The emitter-gold emitter diffusion system was also evaluated for feasibility. 2 Wafer processing. The feasibility of using 1 12 inch wafers with slurry polish and chemical etch was investigated. 3 Wafer storage. Devices which had been stored in N2 for 15 days at various steps were processed and evaluated. 4 Assembly processing. Units were constructed using ultrasonic wire bonding of aluminum wire to bare kovar posts and deionized water boiling prior to encapsulation. 5 Reliability. Completed units were evaluated. Author
- Electrical and Electronic Equipment
- Fabrication Metallurgy