PRODUCTION ENGINEERING MEASURE (PEM) FOR TRANSISTOR, PNP, SILICON, SWITCHING TYPE EL-2N(X-12).
Quarterly rept. no. 2, 25 Jun-25 Sep 65,
TEXAS INSTRUMENTS INC DALLAS SEMICONDUCTOR-COMPONENTS DIV
Pagination or Media Count:
Emphasis during this quarter has been placed on material evaluation h sub FE and h sub fe at 10 mA, switching times, and equipment modification switching jig. Epitaxial layer thickness and resistivity were optimized and effected a significant reduction in collector saturation voltage. V sub CEsat values ranged between 0.33 V and 0.20 V. A reasonable percentage of units attained the 0.25 V maximum specification. If the BV sub CEO requirement is relaxed to 10 V, then the V sub CEsat distribution falls within the 0.25 V limit. The reduction in V sub CEsat improved h sub FE and h sub fe performance at 10 mA. Optimum device performance still occurs at 1 mA, but fall off is not as drastic. Delay time, rise time, and fall time were reduced on the second engineering samples. This was accomplished by a major reduction in parasitic capacitance associated with the switching fixture. Storage time was increased slightly due to the improved performance of d-c h sub FE. Typical values for the second engineering samples are t sub d 3.2 ns t sub r 5.2 ns t sub s 12.5 ns t sub f 6.8 ns. Attempts to improve device gold concentration by liquid nitrogen quenching or increased diffusion temperature failed to produce lower storage times. Author
- Electrical and Electronic Equipment
- Fabrication Metallurgy