Accession Number:

AD0627334

Title:

TRANSISTOR, FIELD EFFECT, INSULATED GATE, 100 MC AMPLIFIER.

Descriptive Note:

Final rept. 1 Dec 64-1 Jun 65,

Corporate Author:

SILICONIX INC SUNNYVALE CALIF

Personal Author(s):

Report Date:

1965-06-01

Pagination or Media Count:

33.0

Abstract:

Three N-channel depletion-mode MOS transistors for use in a 100 mc amplifier were designed, manufactured, and tested. The first two devices, MOS I and MOS II, were designed to study high-frequency characteristics. MOS I had substantially higher transconductance than MOS II and hence more power gain. The best neutralized power gain of MOS I was 14.5 db, limited by low transconductance and high input conductance. MOS III resulted from design changes in MOS I. Neutralized power gain was increased to 19 db with a transconductance of about 2000 micro mhos. The C sub dg was 0.2 pf essentially the pin capacitance of the TO-18 package, C sub gs 3 pf, and C sub ds 1.5 pf. Devices designed under the contract were minimum geometry designs to maximize the g sub fsC ratios. Because of this, the power gain is lower than the 20 db goal set by the contract. It is concluded from this work that the capacitance must be increased slightly to increase the transconductance necessary to guarantee a 20 db power gain. Author

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE