SYNTHESIS OF INPUT EQUATIONS FOR ERRORTOLERANT COUNTERS.
PENNSYLVANIA STATE UNIV UNIVERSITY PARK ORDNANCE RESEARCH LAB
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A computer-oriented procedure was developed to derive the sets of dual-input equations for error-tolerant counters. The counters are composed of J-K Flip-flops interconnected by And-Or logic with an external sequencing pulse. The synthesis procedure involves the selection of terms which satisfy a concise set of distance and intersection properties. The equations are minimized either for the fewest number of Ands and diodes, or for the fewest number of undetectable malfunctions, where an undetectable malfunction is an undetectable control level diode on an And. Approximately 700 counters were synthesized to derive either the configuration using the least amount of equipment or the configuration having the least number of undetectable malfunctions. The counters used either minimum distance three or minimum distance four state assignments to obtain the error-tolerant property.