DETAILED STUDY OF DELETERIOUS EFFECTS ON SILICON TRANSISTORS.
Quarterly rept. no. 3, 29 Apr-28 Jul 64,
MOTOROLA INC PHOENIX ARIZ
Pagination or Media Count:
A complete summary on common emitter DC gain degradation phenomena on NPN transistors is given. The h sub Fe degradation, with respect to nonbias temperature stress, reverse bias plus temperature stress, operating life stress, encapsulating ambient, surface contamination, surface coating, etc., is discussed. Also models for h sub FE degradation are presented. In the second part the reasons why the surface sensitive parameters are not closely correlated are discussed. Author