INTEGRATED LOGIC NETS.
Final rept. for 1 Jul 61-30 Jun 64,
RCA LABS PRINCETON N J
Pagination or Media Count:
Investigations into suitable devices for constructing integrated logic nets led to the development of the MOS metal-oxide-semiconductor transistor. Success in its fabrication was realized through extensions of the wellestablished diffusion and photolithographic techniques used for bipolar-transistor construction. Analysis of the MOS structure has produced a mathematical model that is useful for both optimizing device parameters and calculating circuit performance. Digital circuits constructed of MOS transistors can be eminently simple, thus making feasible the fabrication of large-array integrated logic nets. Complete circuits can be constructed of only MOS transistors and evaporated intraconnections. Electrical instabilities which initially were observed in MOS transistors were shown to be not fundamental to the device alteration of the fabrication process resulted in transistors which exhibited no signs of instability during a 300-hour test period. Recent theoretical and empirical analysis of transistor properties has clarified and confirmed the role played by transistor geometry. In addition, substrate bias voltage was shown to be of value both for increasing pinchoff voltage and for reducing average drain capacitance. Author