FAILURE MECHANISMS IN MICROELECTRONICS.
Quarterly rept. no. 2, Aug-Oct 63
WESTINGHOUSE DEFENSE AND SPACE CENTER BALTIMORE MD
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A series of 12 wafers with 625 devices each, fabricated in P-type, 10.4-ohm-cm silicon was processed through all fabricational stages, and measurements were made on the surface parameters at each stage of fabrication in certain ones device characteristics were measured on individual devices on the wafers as a function of position, and results are being compared with the values of the surface measurement parameters previously obtained for the same device or area on the wafer during the processing stages. This work is continuing, and overall results will be available later. Present indications show variation in characteristics with position on the wafer, and that the two most drastic stages in fabricational processes affecting surface properties are the vapor etch and the photoetch. Evidence was obtained for the existence of insulating subvisible layers over certain windows but none over others in a wafer treated by supposedly uniform developing and photoetch. The relation of these layers to device performance and junction depth is being investigated, since in a complex device it may be a mechanism responsible for variations in characteristic performance or for punchthrough or shorting. Author