CONTENT-ADDRESSABLE MEMORY TECHNIQUES.
Quarterly engineering progress rept. no. 2, 1 Aug-31 Oct 65,
SPERRY RAND CORP PHILADELPHIA PA UNIVAC DIV
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An investigation is reported of the following experimental verification of the current-steering and the readout mechanisms theoretical analyses of the word-loop inductance L, resistance R, and capacitance C parameters and their effect on the current-steering and the readout mechanisms development of a fabrication process for a new memory-plane configuration which has potential advantages over the first plane configuration. The current-steering and the readout mechanisms were successfully demonstrated. A high-power current-steering concept was originated. Theoretical analyses were made for both the low-power and the high-power steering schemes. Results of the analyses indicate that the high-power steering scheme can substantially increase the bit density of a CAM by a factor of about 2.5 to 1 over the low-power scheme. There is a penalty on the search speed which makes the high-power scheme about 30 slower than the low-power scheme. Progress in developing a fabrication process for a new memory-plane configuration was slow. Several methods were tried, but were not considered compatible with the goal of a low-cost, batch-fabrication process. No fundamental difficulty was encountered or anticipated. Author
- Electrical and Electronic Equipment
- Computer Hardware