TECHNOLOGY FOR PNP PLANAR SILICON TRANSISTORS: SWITCHING AND AMPLIFYING
ARMY ELECTRONICS LABS FORT MONMOUTH NJ
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Processes and techniques required for fabrication of experimental planar PNP silicon transistors were developed and demonstrated as feasible. Processes involved include material preparation, antimony base diffusion, boron emitter diffusion, oxide masking, photoresist techniques, simultaneous gold metalizing of emitter and base regions, collector alloy contact and basing, and thermocompression bonding. Initial transistors have typical dc Beta values of 35 to 40 and FT values as high as 350 MCS. Processes described were also used in preliminary fabrication of solid state microcircuit passive components.
- Electrical and Electronic Equipment
- Industrial Chemistry and Chemical Processing