Resolution of Address Information in a Content Addressable Memory.
OFFICE OF THE SECRETARY OF THE ARMY WASHINGTON D C
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The patent describes an address resolver for encoding the addresses of flagged information stored in an electronic memory. A matrix of cross conductors interconnected by diodes in the form of a binary tree has the 2 in. input conductors connected to 2 in. different two-state storage devices and the n output conductors connected to n AND gates. Under the control of a central processor, selected storage devices are set to indicate the location of the flagged information. The diodes are biased in one of two directions depending on whether the storage devices are set or reset. The bias on the diodes is detected by the AND gates and the results are stored in a register to indicate the highest address.