Accession Number : ADA631951


Title :   Hardware Acceleration of Sparse Cognitive Algorithms


Descriptive Note : Final rept. 1 Dec 2014-15 Feb 2016


Corporate Author : NORTH CAROLINA STATE UNIV AT RALEIGH


Personal Author(s) : Franzon, Paul D ; Baker, Lee ; Dey, Sumon ; Li, Weifu ; Schabel, Joshua


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a631951.pdf


Report Date : May 2016


Pagination or Media Count : 46


Abstract : Hardware accelerators were designed for both the Sparsey and Numenta HTM cortical algorithms. Two versions were designed -- a programmable 65 nm SIMD version with Processor in Memory (PiM) extensions and a 65 nm ASIC version. They were compared against a 28 nm GPU baseline using the KTH video action recognition benchmark. Performance/power improvement over the GPU were (Sparsey) SIMD with PiM: 1490; ASIC: 1300; and (HTM) SIMD with PiM: 537; ASIC: 47,100.


Descriptors :   *COMPUTER ARCHITECTURE , *INTEGRATED CIRCUITS , *LEARNING MACHINES , *MEMORY DEVICES , ALGORITHMS , CENTRAL PROCESSING UNITS , COGNITION , COMPLEMENTARY METAL OXIDE SEMICONDUCTORS , COMPUTER PROGRAMMING , INPUT OUTPUT PROCESSING , MULTIPROCESSORS , RANDOM ACCESS COMPUTER STORAGE , SPARSE MATRIX , VIDEO SIGNALS


Subject Categories : Computer Hardware
      Cybernetics


Distribution Statement : APPROVED FOR PUBLIC RELEASE