Accession Number : ADA611771


Title :   Fault Tolerance for VLSI Multicomputers


Descriptive Note : Doctoral thesis


Corporate Author : CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES


Personal Author(s) : Tamir, Yuval


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a611771.pdf


Report Date : Aug 1985


Pagination or Media Count : 154


Abstract : The performance requirements of future high-end computers will only be met by systems that facilitate the exploitation of the parallelism inherent in the algorithms that they execute. One such system is a multicomputer that consists of hundreds or thousands of VLSI computation nodes interconnected by dedicated links. Some important applications of high-end computers, such as weather forecasting, require continuous correct operation for many hours. This requirement can only be met if the system is fault-tolerant, i.e., can continue to operate correctly despite the failure of some of its components. This dissertation investigates the use of fault tolerance techniques to increase the reliability of VLSI multicomputers. Different techniques are evaluated in the context of the entire system, its implementation technology, and intended applications. A proposed fault tolerance scheme combines hardware that performs error detection and system-level protocols for error recovery and fault treatment. Practical design and implementation tradeoffs are discussed. A fault-tolerant system must identify erroneous information produced by faulty hardware. It is shown that a high probability of error detection can be achieved with self-checking nodes implemented using duplication and comparison. The requirements for detecting errors caused by hardware faults are: (1) the comparator is fault-free, and (2) the functional modules never produce identical incorrect outputs. Requirement (1) is fulfilled with a self-testing comparator that signals its own faults during normal operation. An implementation of such a comparator using MOS PLAs is discussed. Requirement (2) is fulfilled with two modules that are implemented differently so that, although they perform identical functions, they have a low probability of failing simultaneously in exactly the same way. Low-cost techniques for implementing such modules are presented.


Descriptors :   *FAULT TOLERANT COMPUTING , COMPARATORS , DISTRIBUTED COMPUTING , FAULT TOLERANCE , HIGH PERFORMANCE COMPUTING , METAL OXIDE SEMICONDUCTORS , MULTIPROCESSORS , PARALLEL PROCESSING , RELIABILITY , THESES , VERY LARGE SCALE INTEGRATION


Subject Categories : Computer Hardware
      Computer Systems
      Computer Systems Management and Standards


Distribution Statement : APPROVED FOR PUBLIC RELEASE