Accession Number : ADA595228


Title :   Logic Encryption


Descriptive Note : Final technical rept. Sep 2011-Sep 2013


Corporate Author : POLYTECHNIC INST OF NEW YORK BROOKLYN


Personal Author(s) : Karri, Ramesh ; Sinanoglu, Ozgur ; Rajendran, Jeyavihayan


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a595228.pdf


Report Date : Feb 2014


Pagination or Media Count : 37


Abstract : Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.


Descriptors :   *CRYPTOGRAPHY , CIRCUITS , COMPUTER SECURITY , LOGIC


Subject Categories : Cybernetics


Distribution Statement : APPROVED FOR PUBLIC RELEASE