Accession Number : ADA495540


Title :   Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation


Descriptive Note : Final rept. 25 Apr 2003-30 Sep 2008


Corporate Author : TEXAS UNIV AT AUSTIN DEPT OF COMPUTER SCIENCES


Personal Author(s) : Keckler, Stephen W ; Burger, Doug ; McKinley, Kathryn S ; Crago, Steve ; Lethin, Richard


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a495540.pdf


Report Date : Sep 2008


Pagination or Media Count : 108


Abstract : The Tera-op Reliable Intelligently Adaptive Processing System (TRIPS) is a novel computer system designed to address technology scaling challenges, to provide high performance through concurrency, and to demonstrate mechanisms for hardware polymorphism. The team has constructed a full-system TRIPS prototype including a new Explicit Data Graph Execution (EDGE) instruction set architecture, custom application-specific integrated circuit (ASIC) chips, system circuit boards, a custom compiler with new optimization capabilities, a software development kit, and support for multithreaded parallel programs. Consisting of approximately 170 million transistors in a 130nm technology, the TRIPS chip includes two coarse grained processors, each with 16 ALUs (including floating-point units) that execute in parallel. TRIPS systems of up to 20 chips have been deployed at UT-Austin, ISI-East, and the Air Force Research Laboratory (AFRL). The prototype demonstrates per-processor performance (measured in cycles) of up to three times better than leading commercial products. Performance analysis results have led to follow-on architectures that employ dynamic polymorphism to tailor the capabilities of the hardware to the demands of the software.


Descriptors :   *PARALLEL PROCESSING , *COMPUTER ARCHITECTURE , CHIPS(ELECTRONICS) , MEMORY DEVICES , PROTOTYPES , SEMICONDUCTOR DEVICES , ALGORITHMS


Subject Categories : Computer Programming and Software
      Computer Hardware


Distribution Statement : APPROVED FOR PUBLIC RELEASE