Accession Number : ADA471474


Title :   Silencer! A Tool for Substrate Noise Coupling Analysis


Descriptive Note : Master's thesis


Corporate Author : OREGON STATE UNIV CORVALLIS SCHOOL OF ENGINEERING


Personal Author(s) : Birrer, Patrick


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a471474.pdf


Report Date : 09 Jan 2004


Pagination or Media Count : 149


Abstract : This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated into the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different levels of hierarchy -- from a level where only an approximate layout of the transistors is known to a level that incorporates various parasitic elements. It can be used for layout optimization to reduce substrate cross-talk noise between circuitry that injects noise into the substrate and other circuitry that is sensitive to it. Examples in a TSMC 0.35 micrometer heavily doped process have been simulated and the results are in good agreement with measured fabricated chips.


Descriptors :   *COMPUTERIZED SIMULATION , *COUPLING(INTERACTION) , *INTEGRATED CIRCUITS , *NOISE(ELECTRICAL AND ELECTROMAGNETIC) , *METAL OXIDE SEMICONDUCTORS , *TRANSISTORS , *NOISE ANALYZERS , COMPUTER PROGRAMS , DIGITAL SYSTEMS , SILICON , DOPING , ANALOG SYSTEMS , CROSSTALK , INDUCTANCE , ELECTRICAL RESISTANCE , SUBSTRATES , MEASUREMENT , OPTIMIZATION , THESES , CHIPS(ELECTRONICS)


Subject Categories : Electrical and Electronic Equipment
      Computer Programming and Software
      Electricity and Magnetism
      Solid State Physics


Distribution Statement : APPROVED FOR PUBLIC RELEASE