Accession Number : ADA461522


Title :   Code Compression for DSP


Corporate Author : MICHIGAN UNIV ANN ARBOR DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE


Personal Author(s) : Lefurgy, Charles ; Mudge, Trevor


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a461522.pdf


Report Date : Dec 1998


Pagination or Media Count : 7


Abstract : Previous works have proposed adding compression techniques to a variety of architectural styles to reduce instruction memory requirements. It is not immediately clear how these results apply to DSP architectures. DSP instructions are longer and have potentially greater variation which can decrease compression ratio. Our results demonstrate that DSP programs do provide sufficient repetition for compression algorithms. We propose a compression method and apply it to SHARC, a popular DSP architecture. Even using a very simple compression algorithm, it is possible to halve the size of the instruction memory requirements.


Descriptors :   *SIGNAL PROCESSING , *DIGITAL SYSTEMS , *COMPRESSION RATIO , ALGORITHMS , CODING , MEMORY DEVICES , REQUIREMENTS


Subject Categories : Computer Hardware
      Miscellaneous Detection and Detectors


Distribution Statement : APPROVED FOR PUBLIC RELEASE