Accession Number : ADA426160


Title :   Tera-Op Reliable Intelligently Adaptive Processing System (TRIPS)


Descriptive Note : Final rept. 19 Jun 2001-31 Mar 2004


Corporate Author : TEXAS UNIV AT AUSTIN DEPT OF COMPUTER SCIENCES


Personal Author(s) : Keckler, Stephen W ; Berger, Doug ; Dahlin, Michael ; John, Lizy ; Lin, Calvin ; McKinley, Kathryn ; Keller, Tom ; Nowka, Kevin


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a426160.pdf


Report Date : Apr 2004


Pagination or Media Count : 29


Abstract : The TRIPS project proposes and evaluates technology for scalable and adaptive computer systems. The TRIPS processor and on-chip memory architectures are designed to handle both the increasing wire delays and power constraints of near-future integrated circuit fabrication technology. Combined with the new TRIPS compiler, the results of detailed architectural models show that the TRIPS system can achieve performance improvements by up to an order of magnitude over that of conventional architectures (at comparable clock rates) on applications ranging from signal processing to threaded server workloads. TRIPS innovations also include low-power circuits, such as latches and digital phase-locked loops, that will be required for future high-performance polymorphous chips such as TRIPS. Static power analysis tools were also developed to better estimate and balance power consumption in multiple modes of operation. The results of the proof-of-concept phase of TRIPS have shown substantial scientific promise, justifying


Descriptors :   *COMPUTER ARCHITECTURE , *CHIPS(ELECTRONICS) , *MEMORY DEVICES , SIGNAL PROCESSING , LOW POWER , DIGITAL SYSTEMS , PARALLEL PROCESSING , SCALING FACTOR , ADAPTIVE SYSTEMS , WORKLOAD , ENERGY CONSUMPTION , PHASE LOCKED SYSTEMS , MULTIPLE OPERATION


Subject Categories : Computer Systems Management and Standards


Distribution Statement : APPROVED FOR PUBLIC RELEASE