Accession Number : ADA266930


Title :   The Application of Compiler-Assisted Multiple Instruction Retry to VLIW Architectures


Corporate Author : ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB


Personal Author(s) : Chen, Shyh-Kwei ; Fuchs, W K ; Hwu, Wen-Mei W


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a266930.pdf


Report Date : Jan 1993


Pagination or Media Count : 19


Abstract : Very Long Instruction Word (VLIW) architectures enhance performance by exploiting fine instruction level parallelism. In this paper, we describe the development of two compiler assisted multiple instruction word retry schemes for VLIW architectures. The first scheme utilizes the compiler techniques previously developed for processors with single functional units. Compiler generated hazard-free code with different degrees of rollback capability for uni- processors is compacted by a modified VLIW trace scheduling algorithm. Nops are then inserted in the scheduled code words to resolve data hazards for VLIW architectures. Performance is compared under three parameters : N, the rollback distance for uni-processors; P, the number of functional units; and n, the rollback distance for VLIW architectures. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards. Performance results are shown for six benchmark programs Fault-tolerant parallel computing, Instruction retry, Compilers, VLIW Architectures, Instruction level parallelism


Descriptors :   *COMPUTER ARCHITECTURE , *COMPUTER AIDED INSTRUCTION , *COMPILERS , ALGORITHMS , BUFFERS , PARALLEL PROCESSING , FAULT TOLERANT COMPUTING , INSTRUCTIONS , SCHEDULING , HAZARDS , PARAMETERS


Subject Categories : Computer Programming and Software


Distribution Statement : APPROVED FOR PUBLIC RELEASE