Accession Number : ADA262614


Title :   Design of a Hardware Discrete Event Simulation Coprocessor


Descriptive Note : Master's thesis


Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSONAFB OH SCHOOL OF ENGINEERING


Personal Author(s) : Daniel, David W


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a262614.pdf


Report Date : Mar 1993


Pagination or Media Count : 150


Abstract : A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design objective... . Simulation, Parallel processing, Discrete event simulation, VHDL, Coprocessor, Simulation accelerator.


Descriptors :   *COMPUTER ARCHITECTURE , *PARALLEL PROCESSORS , *SYNCHRONIZATION(ELECTRONICS) , ALGORITHMS , DATA PROCESSING , SIMULATION , THESES , PARALLEL PROCESSING , TARGETS , NODES , LOW LEVEL , SUBROUTINES


Subject Categories : Electrical and Electronic Equipment
      Computer Hardware


Distribution Statement : APPROVED FOR PUBLIC RELEASE