Accession Number : ADA260754


Title :   VLSI for High-Speed Digital Signal Processing


Descriptive Note : Quarterly progress rept. 1 Oct-31 Dec 1992


Corporate Author : CALIFORNIA UNIV LOS ANGELES


Personal Author(s) : Willson, Jr, Alan N


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a260754.pdf


Report Date : 31 Dec 1992


Pagination or Media Count : 10


Abstract : During the past quarter we have fabricated and tested a 12-bit by 16- bit multiplier based on our previous multiplier architecture but using third order recoding. That is, we use an 8-to-1 multiplexer selected by 3 input bits to form each partial products instead of the 4-to-1 multiplexer selected by 2 input bits as used previously. The partial products (1X, 3X, 5X, and 7X the coefficient value) are stored in an on-chip RAM. Fig. 1 shows the architecture of the test.


Descriptors :   *SIGNAL PROCESSING , *VERY LARGE SCALE INTEGRATION , *MULTIPLEXING , *CHIPS(ELECTRONICS) , FABRICATION , INTEGRATED CIRCUITS , RANDOM ACCESS COMPUTER STORAGE , NAVAL RESEARCH


Subject Categories : Electrical and Electronic Equipment


Distribution Statement : APPROVED FOR PUBLIC RELEASE