Accession Number : ADA258999


Title :   Parallel Simulation of Structural VHDL Circuits on Intel Hypercubes


Descriptive Note : Master's thesis


Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING


Personal Author(s) : Breeden, Thomas A


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a258999.pdf


Report Date : Dec 1992


Pagination or Media Count : 168


Abstract : Many VLSI circuit designs are too large to be simulated with VHDL in a reasonable amount of time. One approach to reducing the simulation time is to distribute the simulation over several processors. This research creates an environment for designing and simulating structural VHDL circuits on the Intel iPSC/2 and iPSC/860 Hypercubes. Logic gates and system behaviors are partitioned among the processors, and signed changes are shared via event messages. Circuit simulations are run over the SPECTRUM parallel simulation testbed, and the null- message paradigm is used to avoid deadlock. Structural circuits ranging from forty to over one thousand logic gates are correctly simulated. Although no attempt is made to find optimal partitioning strategies, speedups are obtained for some configurations.


Descriptors :   *MICROPROCESSORS , SIMULATION , THESES , VERY LARGE SCALE INTEGRATION , GATES(CIRCUITS) , INTEGRATED CIRCUITS , CONFIGURATIONS , LOGIC


Subject Categories : Computer Hardware


Distribution Statement : APPROVED FOR PUBLIC RELEASE