Accession Number : ADA257415


Title :   An MCM/Chip Concurrent Engineering Validation.


Descriptive Note : Quarterly rept. no 3, Jul-Sep 1992,


Corporate Author : MICROELECTRONICS AND COMPUTER TECHNOLOGY CORP AUSTIN TX


Personal Author(s) : Moreno, Hector


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a257415.pdf


Report Date : 30 Sep 1992


Pagination or Media Count : 26


Abstract : A software link was established between three commercially available Multi-Chip Module design systems: Allegro, EDGE and Finesse. The link was implemented through a database system based on the ROSE system developed under the sponsorship of the DICE program. The code was written in C++ and uses various methods to feed the information in and obtain It out of the design systems: IGES for Allegro, SKILL for EDGE and d-file for Finesse. The DDR2 (Digital Drop Receiver, version 2) multi-chip module from Harris has been entered into the system and routed, and the Information transferred to all the designers through the ROSE database. Concurrent Engineering, Multi-Chip Module, Computer-Aided Design.


Descriptors :   *COMPUTER AIDED DESIGN , *CONCURRENT ENGINEERING , DATA BASES , ENGINEERING , DROPS , RECEIVERS , COMPUTERS , EDGES


Subject Categories : Computer Programming and Software


Distribution Statement : APPROVED FOR PUBLIC RELEASE