Accession Number : ADA256306


Title :   A Complete-Time Approach for Chaining and Execution Control in the AN/UYS-2 Parallel Signal Processor


Descriptive Note : Master's thesis


Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA


Personal Author(s) : Bell, Harold A


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a256306.pdf


Report Date : Jun 1992


Pagination or Media Count : 78


Abstract : The AN/UYS-2 represents the U.S. Navy's effort to meet the signal processing demands of the 21st at century. It is programmed using the Processing Graph Methodology (PGM), where signal processing applications are represented as graphs and the nodes specify library primitives. Presently the AN/UYS-2 incorporates a First-Come-First-Serve run-time technique to allocate system resources to support large-grain data-flow execution. While this technique results in low run-time overhead, the system throughput degrades rapidly under high system load. To provide uniform output even under high load, a compile-time technique, called Revolving Cylinder (RC) analysis, is developed further to identify optimal chains and restructure the graph. It is shown by simulation that such chaining and restructuring improve the overall system performance. Digital system processing, Compile-time analysis, Revolving cylinder, AN/UYS-2, Data-flow processing, Processing graph methodology, Signal processing, Scheduling, Large-grain data-flow architecture.


Descriptors :   *SIGNAL PROCESSING , *DATA PROCESSING EQUIPMENT , OUTPUT , SIMULATION , DIGITAL SYSTEMS , METHODOLOGY , INFORMATION TRANSFER , PROCESSING , GRAPHS , COMPUTER ARCHITECTURE , NODES , TIME , SCHEDULING , SIGNALS , THROUGHPUT , RESOURCES , DATA RATE


Subject Categories : Computer Hardware


Distribution Statement : APPROVED FOR PUBLIC RELEASE