Accession Number : ADA255013


Title :   Testing and Fault-Tolerant Design Techniques for Advanced Digital Architectures


Descriptive Note : Final technical rept. 1 Jan 1989-31 Dec 1991


Corporate Author : TEXAS UNIV AT AUSTIN


Personal Author(s) : Malek, Miroslaw ; Mercer, M R


Full Text : https://apps.dtic.mil/dtic/tr/fulltext/u2/a255013.pdf


Report Date : 31 Dec 1991


Pagination or Media Count : 10


Abstract : We have continued working on our new concept, topological testing, and demonstrated several applications in the area of multiprocessor testing. Topological testing uses graph theoretic optimization methods, such as the Traveling Salesman Problem, the Chinese Postman Problem, coloring, path covering and partitioning to minimize the test time. The topological testing techniques can be applied to test a system's behavior and its organization at each level of the system's hierarchy; namely, circuit, logic, register transfer, instruction and processor-memory-switch levels. Specifically, the topological testing approach was demonstrated by developing tests for the multistage interconnection network and the hypercube network. We have also developed optimal test sets for mesh networks and further increased a test coverage by including solutions for priority circuits.


Descriptors :   *FAULT TOLERANT COMPUTING , OPTIMIZATION , TOPOLOGY , MULTIPROCESSORS , SYSTEMS ANALYSIS , COMPUTER NETWORKS


Subject Categories : Computer Hardware


Distribution Statement : APPROVED FOR PUBLIC RELEASE