Accession Number : ADA185847
Title : Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics.
Descriptive Note : Doctoral thesis,
Corporate Author : ILLINOIS UNIV AT URBANA COLL OF EDUCATION
Personal Author(s) : Su, Shun-Lin
Report Date : Sep 1987
Pagination or Media Count : 165
Abstract : As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized. In this research, two programs, FEMRC and HPEX, have been developed to investigate the following areas: (1) interconnect modeling, (2) hierarchical parasitic circuit extraction, and (3) collapsing technique for interconnects. The FEMRC is a two-dimensional, finite-element program which computes the resistance or the capacitance from the user-specified geometry. Since the equation formulation for FEMRC is based on a finite-element method, there is no shape restrictions on dielectric interfaces or conductor geometries. In resistance calculation, a quasi-three-dimensional effect of contact resistance is also taken into account. The program HPEX is a hierarchical parasitic circuit extractor which takes the CIF layout description as an input and generates a SPICE input with different details of interconnect parasitics. In this extractor, analytical formulas fitted from numerical data are used to model interconnect parasitics of VLSI circuits in order to compromise between the accuracy and the computation time. Simulations show that by carefully fitting data analytical formulas can be very accurate, especially when the interconnect region is fairly regular.
Descriptors : *CAPACITANCE , *CIRCUITS , *COMPUTATIONS , *DIELECTRICS , *RESISTANCE , ACCURACY , COLLAPSE , DELAY , EQUATIONS , EXTRACTION , FINITE ELEMENT ANALYSIS , FORMULATIONS , INTERFACES , MODELS , SHAPE , SIGNALS , TIME , INTEGRATED CIRCUITS , METAL OXIDE SEMICONDUCTORS , CIRCUIT INTERCONNECTIONS , THESES
Subject Categories : Electrical and Electronic Equipment
Solid State Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE