Accession Number : ADA155043
Title : Design of a Sixteen Bit Pipelined Adder Using CMOS Bulk P-Well Technology.
Descriptive Note : Master's thesis,
Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Personal Author(s) : Reid,W R
Report Date : Dec 1984
Pagination or Media Count : 117
Abstract : The design of a sixteen-bit pipelined adder complementary metal oxide semiconductor circuit is presented. The adder is designed to maximize throughput and to provide for testability. Tutorial material on CMOS design is also presented. Additional keywords: theses; VLSI(very large scale integration); computer aided design; NMOS(negatively doped metal oxide semiconductors); logic circuits. (Author).
Descriptors : *LOGIC CIRCUITS , COMPUTER AIDED DESIGN , TEACHING METHODS , THESES , THROUGHPUT , INSTRUCTIONS , COMPLEMENTARY METAL OXIDE SEMICONDUCTORS
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE